This invention relates in general to the field of semiconductor device packaging, and more particularly to a ball grid array package and method using enhanced power and ground distribution circuitry.
The use of ball grid arrays (BGAs) to package electronic circuits and devices such as integrated circuit chips is becoming more prevalent. BGA packaging has proven to provide substantial advantages over other packaging techniques such as, for example, dual in-line packages (DIPs), pin grid array (PGA) packages, tape carrier packages (TCPs), and quad flat packs (QFPs). The advantages of BGA packaging become especially significant when used to package an integrated circuit chip or die having a high pin count and when used to package devices employing high frequency signals. BGA packaging provides the additional advantage of being able to use conventional surface mount technologies (SMTs) and assembly techniques when mounting to a printed circuit board (PCB).
A BGA package generally includes a die or chip, one or more substrate layers provided on top of one another and aligned through a cavity portion, an array of solder balls for providing an electrical and mechanical connection external to the BGA package, and a heat spreader/stiffener for providing a thermal conduction path to cool the die and to provide mechanical support and rigidity to the. BGA package. The substrate layers include various metal layers and traces that serve as signal and/or power distribution connections in addition to distinct signal and power planes. Each of the solder balls of the array of solder balls electrically couple to either ground pads, power pads, or signal pads on the exposed substrate. Solder balls may also couple to sacrificial pads that are provided for mechanical advantages and do not provide an electrical connection to the package. The electrical connections are generally made through vias or metallized interconnections provided through the various substrate layers. The fabrication of the various vias and substrate layers is expensive and time consuming and reduces the overall packaging yield and reliability of high pin-count packages.
The die is generally mounted on the heat spreader/stiffener using an adhesive or glue such as an epoxy. The various bond pads of the die are electrically coupled to the various solder balls of the array of solder balls by coupling to either the ground plane, the power plane, or to a corresponding signal trace provided by the signal plane. The connection is generally provided using wire bonding techniques. These connections are expensive and complicated by the fact that connections must be made a with multiple substrate layers.
The fabrication of the multiple metal layers, traces, and multiple substrate layers is expensive. The complexity and cost of BGA packages are also influenced by the number of signal layers and vias that must be provided in the various substrate layers to provide a path to connect the solder balls to either the ground plane, the power plane, or a desired signaling lead of the signal plane. In general, multiple substrate layers and multiple vias result in lower BGA package fabrication yields and higher costs. The formation of the vias create additional complexity and cost because each of the vias generally require the formation of a conductive layer, such as a metal layer on the internal walls of the via, to ensure a complete electrical path. This may be referred to as metallization. The metallization of the internal walls of each. via increases the overall complexity and cost of manufacturing multiple substrate layer BGA packages.
From the foregoing it may be appreciated that a need has arisen for a ball grid array substrate and method, that uses a single substrate layer having a metal layer on each side thereby eliminating the need to provide multiple substrate layers and associated multiple metal layers while maintaining a high level of electrical performance. In accordance with the present invention, a ball grid array substrate and method are provided which substantially eliminate the disadvantages and problems outlined above.
According to the present invention, a ball grid array substrate is provided that includes a substrate dielectric, a power ring, a ground ring, a plurality of traces, and a metal layer. The substrate dielectric has a first side, a second side, and a cavity formed therein. The power ring, the ground ring, and the plurality of traces are provided on the first side of the dielectric. The metal layer is provided on the second side of the substrate dielectric and is electrically coupled to the first side. In one embodiment, the metal layer serves as the ground plane and electrically couples with the ground ring and select traces of the plurality of traces that serve as ground connections. In another embodiment, the metal layer serves as the power plane and electrically couples with the power ring and the select traces of the plurality of traces,that serve as power connections.
According to another aspect of the present invention, a method for forming a structure, such as a ball grid array substrate and package, is provided. The method includes the step of providing a substrate having a first metal layer on a first side of a substrate dielectric, and a second metal layer on a second side of the substrate dielectric. The method further includes the steps of forming a power ring, a ground ring, and a plurality of traces on the first metal layer. Each of the plurality of traces serving as either a ground connection, a signal connection, or a power connection. Next, the method includes forming a cavity in the substrate. Finally, the method includes the step of forming vias that couple portions of the first metal layer to the second metal layer.
In alternative embodiments, the method for forming a structure of the present invention includes additional steps to form a ball grid array package. In such a case, the method includes the steps of mounting the substrate to a heat spreader/stiffener and mounting a die to the heat spreader/stiffener through the cavity in the substrate. Next, the method includes the step of coupling a die bond pad of the die to the first metal layer, such as a signal die bond pad to a signal trace. Finally, the method includes the step of sealing the die cavity and forming solder balls to attach to the first metal layer.
The present invention provides myriad technical advantages. One technical advantage of the present invention includes the elimination of multiple substrate or substrate dielectric layers. Multiple layers increase the overall complexity and costs of BGA packages while reducing overall yield. Another technical advantage of the present invention includes the minimization of substrate vias, the elimination of signal connection vias, and a novel layout that allows multiple connections, such as ground connections, to be electrically coupled using minimal or shared vias to minimize overall fabrication costs. Yet another technical advantage of the present invention includes enhanced electrical characteristics by providing an active ground plane at a desired distance from a signal plane so that signal line impedance may be controlled as desired. In this manner, overall device performance is enhanced by providing lower lead or trace inductances and capacitances with minimized cross-talk. This is especially important when using BGA packaging with a die or chip operating at a high frequency and having a high pin count or I/O count. Still yet another technical advantage includes a common power ring and a common ground ring that provides a versatile wire bond interconnect to the die as needed. Other technical advantages are readily apparent to one skilled in the art from the following figures, description, and claims.